FIG. 8 is a circuit diagram of a semiconductor memory device including conventional static memory cells MC. The semiconductor memory device of this type employs memory cells MC having the structure shown in FIG. 3, 4 or 5.
The memory cell MC of FIG. 3 has access transistors (N channel) TAN1 and TAN2, drive transistors (N channel) TAN3 and TAN4, and load transistors (P channel) TAP1 and TAP2.
The memory cell MC of FIG. 4 is of a load resistor type, and has access transistors (N channel) TBN1 and TBN2, drive transistors (N channel) TBN3 and TBN4, and load resistors TBP1 and TBP2.
The memory cell MC of FIG. 5 has access transistors (N channel) TCN1 and TCN2, drive transistors (N channel) TCN3 and TCN4, and load thin-film transistors (P channel) TCP1 and TCP2.
As illustrated in FIG. 8, each column in the semiconductor memory device includes a pair of bit lines B and B, transistors (N channel) TN5, TN6 and TN7 for pulling up the bit lines B and B in a standby state, transistors (N channel) TN1 and TN2 for preventing stored data from being lost when writing data, a column decoder CD and an inverter INV, CMOS transfer gates TG1 and TG2 for selecting a column. The CMOS transfer gate TG1 includes an MOS transistor (N channel) TN3 and an MOS transistor (P channel) TP1. The CMOS transfer gate TG2 includes an MOS transistor (N channel) TN4 and an MOS transistor (P channel) TP2.
One end of the bit line B and of the bit line B are connected to a data lines D and D through the CMOS transfer gate TG1 and TG2, respectively. The other end of the bit line B and of the bit line B are connected to power supply lines PSL through the transistors TN5 and TN6, respectively. The bit line B and the bit line B are connected with the transistor TN7 and a plurality of memory cells.
The output of the column decoder DC goes high only when its own column address is input. The high state of the output turns on the CMOS transfer gates TG1 and TG2.
In a conventional semiconductor memory device, in a column other than a selected column, a line CS connected to the output terminal of the inverter INV goes high, and the transistors TN1 and TN2 are turned on. When a write operation is started on the selected column, the bit line of the column is caused to make a big swing (i.e., the voltage level is changed significantly) by a write signal supplied by a write driver (not shown). Since the capacity between bit lines becomes larger, noise appears in the bit lines of adjacent unselected columns.
At this time, the bit lines B and B of the unselected columns go high. The reason for this is that a voltage is applied from the power source to the bit lines B and B of the unselected columns via the load elements (load transistors TAP1 and TAP2, the load resistors TBP1 and TBP2, or the load thin-film transistors TCP1 and TCP2) in the memory cells MC and the transistors TN1 and TN2.
The voltage level supplied from the memory cells MC to the bit lines B and B of the unselected columns is relatively low because of a voltage drop caused by the load elements in the memory cells MC. Therefore, the voltage level of the bit lines B and B of the unselected columns is raised by supplying a source voltage to the bit lines B and B of the unselected columns via the transistors TN1 and TN2. This arrangement restrains an increase in the amount of noise occurred in the bit lines B and B of the unselected columns during a write operation, preventing the data stored in the memory cells from being lost.
To restrain power consumption (i.e., leakage of direct currents), the driving power (the value of drain current) of the transistors TN1 and TN2 is arranged to be much lower than that of the drive transistors (TAN3 and TAN4, TBN3 and TBN4, or TCN3 and TCN4) in the memory cells MC.
In order to allow the write driver to properly perform its operation, the line ATD connected to the respective gates of the transistors TN5, TN6 and TN7 is kept low, and the transistors TN5, TN6 and TN7 is kept off.
In recent years, to increase the capacity of semiconductor devices, the devices have finer patterns. And, the rate of fault occurring in the bit lines increases. One type of common faults is a short circuit between bit lines. Another types of faults are bit lines fixed to the power source potential caused by a short circuit between the bit line and a power supply line, and bit lines fixed to a ground potential caused by a short circuit between the bit lines and the ground potential section.
In order to cope with such a fault, with a prior art, a single chip is divided into a plurality of blocks and a block having a fault (hereinafter referred to as a faulty block) is replaced with a redundant block. More specifically, when a fault is detected in a product test, the transistors TN5, TN6 and TN7 in the faulty block are turned off, and a redundant block is used instead of the faulty block. This allows semiconductor memory devices having faults to be corrected.
However, with a conventional structure, the transistors TN1 and TN2 are on in a standby state and a direct current path from the power source potential to the ground potential is produced, thereby increasing the leakage direct currents. It is therefore impossible to fully correct a semiconductor memory device having a fault caused by a short circuit between bit lines and a ground potential section.
Moreover, in the semiconductor memory device, if the transistors TN1 and TN2 are removed, the amount of noise occurring in the bit lines B and B of an unselected column increases during a write operation, causing the data stored in the memory cell to be lost.
In order to prevent such a drawback, the transistors TN1 and TN2 may be arranged to be turned on only when a block on which a write or read operation is to be performed is selected. However, this structure causes an error during the read operation. Namely, in the selected block, the transistors TN1 and TN2 are turned on and the bit lines B and B go high. This causes the potential difference between the bit lines B and B to be diminished when reading out data, preventing the data from being properly read.